The present invention relates to a method for manufacturing a semiconductor device capacitor. More particularly, the present invention relates to a method for readily manufacturing a semiconductor device capacitor having increased capacitance.
As integration of dynamic random access memory (DRAM) devices increases, various methods for forming the memory cell capacitor structure in three dimensions have been proposed which increase capacitance in the evermore restricted area apportioned to each memory cell. Among the proposed three-dimensional capacitor structures, the cylindrical capacitor structure has typically been adopted for use in semiconductor memory devices having an overall memory size in excess of 64 Mbits. This selection has been made because the interior surface of the cylinder structure as well as the outer surface thereof can be utilized as an effective capacitor area.
FIG. 1 is a section view illustrating a method for manufacturing a cylindrical capacitor structure according to a conventional method. Referring to FIG. 1, a silicon nitride layer 11 is formed over a semiconductor substrate 1 proximate a transistor and a bit line 10. Then, an oxide film pattern 16 is formed in this region expect for an area wherein a capacitor storage node will subsequently be formed. A polysilicon sidewall electrode 17 is formed over the resultant structure, and the area in which the capacitor storage node structure, and the area in which the capacitor storage node will be formed is filled with a photoresist 18. An upper portion of polysilicon sidewall electrode 17 overlaying the oxide film pattern 16 is etched away, and oxide film pattern 16 and photoresist 18 are thereafter removed.
In a highly integrated memory cell, spacing between adjacent cells must be minimized in order to increase the capacitance of the memory cell capacitor by maximizing the capacitor's surface area. As seen in the above-described conventional method, individual memory cell capacitance is restricted by the size, i.e., the width, of oxide film pattern 16 which is used to separate adjacent capacitors. In the foregoing conventional method, the minimally obtainable width of oxide film pattern 16 is limited by the exposure line width of a photo-lithography process.
A crown-shaped cell structure proposed by Toru Kaga et al. provides increased capacitance by forming a crown-shaped cylindrical electrode having double walls. See, "Crown-shaped Stacked-capacitor Cell for 1.5 V Operation 64 Mb DRAMs," IEEE Transactions on Electron Devices, 1991.
The method for manufacturing the crown-shaped cell is generally characterized as follows. First, a first polysilicon layer is formed on a semiconductor substrate on which an oxide film pattern defines the area in which a capacitor storage node is to be formed. Then, an oxide film spacer is formed on the sidewalls of the first polysilicon layer. Then, a second polysilicon layer is formed, and a groove formed by the second polysilicon is filled with an oxide film. The first and second polysilicon layers are etched using the oxide films as an etching block layer, to thereby form a double-cylindrical storage node.
However, in the foregoing method for manufacturing a crown-shaped cell, it is still impossible to form an oxide film pattern defining the area in which a storage node is to be formed having a size smaller than the limiting exposure line width. Therefore, the space between adjacent capacitors cannot be effectively reduced. Moreover, in the foregoing method for manufacturing a crown-shaped cell, an additional process step of filling the groove formed by the second polysilicon layer is required in order to prevent the connection point between the semiconductor substrate and the storage node from being etched away.